People

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Mark Hempstead

After graduating from Tufts University with a BS in Computer Engineering, he entered the Ph.D. program in the School of Engineering and Applied Sciences at Harvard University. He was a member of Harvard University in the VLSI Mixed Signal Group under Prof. Gu-Yeon Wei and the Computer Architecture group under Prof. David Brooks (co-advised) until his graduation in June 2009.  Before beginning his faculty post at Drexel University in January 2010,  he spent 5 months in the R&D department at ARM Ltd. in Cambridge UK.

His research group at Drexel investigates methods to increase energy efficiency across the boundaries of circuits, architecture, and systems. Currently, they are exploring the performance and energy benefits of heterogeneity in future microprocessor architectures. Recent accomplishments include an accelerator architecture for ultrasound imaging, evaluation of hardware reference counting, hardware and operating system support for power-agile computing, and memory systems for accelerator-based architectures. See the Publications page for more information.

Steven Battle

Steve is interested in heterogeneous core design and register management techniques for improving performance and energy efficiency of out-of-order cores. He received a BSc in Electrical and Systems engineering from the University of Pennsylvania in 2003 and an MSc in Microelectronic Engineering from Columbia University in 2004. Before starting at Drexel, Steve worked at IBM as a circuit design engineer on their high performance Z-series mainframe processors (z10 – z12). In 2012, he interned at Samsung’s Austin Research center working on a novel power-characterization methodology for their custom ARM cores.

More info can be found here: http://www.strikingly.com/sbattle

Siddharth Nilakantan

Siddharth’s research interests include Platform-independent workload characterization, Scalable simulation for Many-core Architectures, and utilization of Heterogeneous execution environments. Siddharth completed his Bachelors in Electronics & Communication at M.S. Ramaiah Institute of Technology, Bangalore, India in 2006 and his Masters in Electrical Engineering (VLSI) at the University of Southern California in 2008. Before joining Drexel to pursue his Ph.D. he worked as a Circuit Design Engineer in Novelics, a startup company specializing in Embedded Memory Design. While at Novelics, he worked on the SRAM and DRAM solutions in the 65nm technology node.

Rizwana Begum

Rizwana obtained her B.E. in Electrical and Electronics Engineering from Birla Institute of Technology and Science (BITS-Pilani), India. Before joining Drexel, she spent two years at Qualcomm as Firmware Engineer. During her tenure at Qualcomm she worked on low power architecture design and evaluation of video accelerators. She joined Drexel as a Master’s student in Computer Engineering and currently pursuing first year of her Ph.D. in Electrical and Computer Engineering. Her research interests include low power architectures, energy proportional computing and power modeling. She is currently exploring hardware and operating system support to achieve energy proportionality in mobile platforms.

She was a recipient of Suryadevara Basavaiah Family Educational Fund.She also received university merit scholarship for full academic coursework during her undergraduate studies. She was honored with Gold medal for securing top rank in her 12th grade.

Marko Jaćović

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Marko graduated with a B.S. in Electrical Engineering from Drexel University in 2013.  He currently is pursuing an M.S. in Electrical Engineering/Telecommunications from Drexel University with an anticipated graduation date of June 2015. His research interests are primarily in Telecommunications and Digital Signal Processing.

Tianyun Zhang

Tianyun obtained his B.E. in Software Engineering and M.S. in Computer Science in 2009 and 2012 from Fudan University, Shanghai, China.  He is currently a first year Ph.D. student in Computer Engineering at Drexel University, and his research interests include latency-tolerant microarchitecture, low-power memory systems, and NoCs.

Jason Palaszewski

Jason received his B.S. in Computer Engineering from The College of New Jersey in 2012. His research interests include performance estimation for CPUs and power estimation for GPUs.

Jonathan Stokes

Jonathan graduated from the University of Rhode Island in 2012 with a B.S. in Electrical Engineering. He is currently a first year PhD. student at Drexel, and his research interests include system modeling and telecommunications.